The present invention relates to a CMOS logic circuit, and more particularly but not exclusively to a CMOS logic circuit for use as a line driver.
The well known problem when driving capacitive loads in integrated circuits, such as capacitive lines, is to provide a rapid transition in voltage on the line. One requirement for achieving this aim is to provide an output circuit having a high current capacity but it is also important to drive the output circuit itself with fast transitions in such a way as to enable the output circuit to behave optimally.
One of the problems with known driver circuits is that logic elements in the driver circuitry are required to respond rapidly to both positive-going and negative-going transitions to operate the output circuitry: fast circuitry tends to have small dimensions, and thus low current capacity.
It is an object of the present invention to at least partly overcome the problems of the prior art.
According to a first aspect of the present invention there is provided a CMOS logic circuit having plural inputs and a circuit output, the logic circuit having a first stage and a second stage, the first stage receiving the plural inputs and providing two first stage outputs, the second stage having an output node connected to said circuit output and two current paths connected between said output mode and a reference voltage-receiving node, each of said current paths being substantially identical, and having a first transistor connected to said output node and a second transistor connected to said voltage-receiving node, said first and second transistors being connected in series, wherein each of said first stage outputs is coupled to the control gates of a first transistor in a respective one of said current paths and a second transistor in a respective other current path.
According to a second aspect of the present invention there is provided a CMOS logic circuit having plural inputs and a circuit output, the logic circuit having a first stage and a second stage, the first stage receiving said plural inputs and providing a first stage output, the second stage receiving a first stage output and providing a second stage output which is coupled to said circuit output, wherein the first stage comprises plural two input logic gates, each of said logic gates being configured to have a higher current capability in response to an input transition of one polarity than to an input transition of the opposite polarity, such that said transition of said one plurality causes said circuit output to assume a first logic value, and said second stage having a control input, the second stage being configured to have a higher current capability in response to a first polarity transition at said control input than to a second opposite polarity transition at said control input, wherein said first polarity transition causes said circuit output to assume a second logic value opposite to said first logic value.
Preferably the first stage output is coupled to an inverter for driving an output capacitive load.
Advantageously said second stage comprises two current paths connected between said second stage output and a reference voltage-receiving node, each of said current paths having a first transistor connected to said second stage output and a second transistor connected to a reference voltage-receiving node, wherein said first and second transistors are connected in series, and said first stage has two outputs each of said outputs being coupled to the control gates of a first transistor and a respective one of said current paths and a second transistor in a respective other current path, said control input comprising said reference voltage-receiving node.
Preferably said first stage comprises a plurality of CMOS logic gates, each of said gates having P conductivity transistors and N conductivity transistors, wherein the width of the P conductivity transistors is larger than the width of the N transistors
Preferably the first and second transistors of the second stage are N conductivity transistors, and said second stage further comprises at least one P transistor wherein the width of the N conductivity transistors is substantially greater than that of the P transistor.
According to a third aspect of the present invention there is provided a CMOS logic circuit for driving a capacitive load, having an input circuit and an output circuit, the output circuit having an output to which, in use, said capacitive load is connected the input circuit having at least one CMOS logic gate comprising P and N conductivity transistors, wherein the width of the P conductivity transistors is substantially greater than that of the N conductivity transistors whereby said input stage provides transitions at the output of the output stage into said capacitive load which are faster in one sense than in the other sense and said output circuit comprises P conductivity and N conductivity transistors receiving an output from said input stage and further receiving a control input, whereby the dimensions of said P and N type transistors of said output stage are selected to provide faster output transitions into said capacitive load in said second sense than in said first sense.